High-speed MOSFET, MODFET and HEMT have been proposed in recent years in which an epitaxially grown strained Si layer interposed with an SiGe (silicon-germanium) layer on an Si (silicon) substrate is used for the channel region. In this strained Si-FET, tensile strain occurs in the Si layer due to the SiGe having a larger lattice constant than the Si, and as a result, the band structure of the Si changes, degeneration is removed and carrier mobility increases. Thus, as a result of using this strained Si layer as a channel region, speed can be increased to about 1.3 to 8 times faster than ordinary speeds. In addition, since ordinary Si substrates manufactured by the CZ method can be used for the substrates, high-speed CMOS can be realized with a conventional CMOS process.
However, although epitaxial growth of a high-quality SiGe layer on an Si substrate is required for epitaxial growth of the aforementioned strained Si layer that is desired to be used as the channel region of an FET, due to the difference in the lattice constants between Si and SiGe, there were problems with crystallinity due to dislocation and so forth. Consequently, the following types of proposals have been made in the prior art.
Examples of methods that have been proposed include a method that uses a buffer layer in which the Ge composite ratio of SiGe is changed at constant, gradual increments, a method that uses a buffer layer in which the Ge (germanium) composite ratio is changed in steps, a method that uses a buffer layer in which the Ge composite ratio is changed in the form of a super lattice, and a method that uses a buffer layer in which the Ge composite ratio is changed at a constant increment using an Si off-cut substrate (in, for example, U.S. Pat. No. 5,442,205, U.S. Pat. No. 5,221,413, PCT WO98/00857 and Japanese Unexamined Patent Application, First Publication No. 6-252046).
However, the aforementioned examples of the prior art still had the problems described below.
Namely, since the aforementioned examples of the prior art still exhibits a high penetrating dislocation density on the wafer surface, there is still a need to decrease penetrating dislocation density in order to prevent transistor operation defects. In addition, although various types of heat treatment have been deployed in the process of producing a device on an SiGe layer or Si layer and so forth deposited thereon, there was the problem of the occurrence of worsening of surface or interface roughness of the SiGe layer and Si layer during the heat treatment.